CME_LVDS_example_user_guide_EN01

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LVDS Example

User Guide

04/2014

Capital Microelectronics, Inc.

China

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User Guide of LVDS example

Contents

Contents ..................................................................................................................................................2 1

2 Introduction ......................................................................................................................................3 The example detail ............................................................................................................................4

2.1 Function description ............................................................................................................................. 4

2.1.1 Example 1 ......................................................................................................................................... 4

2.1.2 Example 2 ......................................................................................................................................... 6

2.2 Pin description ...................................................................................................................................... 9

2.2.1 Example 1 ......................................................................................................................................... 9

2.2.2 Example 2 ....................................................................................................................................... 10

Revision History ..................................................................................................................................... 11

2

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User Guide of LVDS example 1 Introduction

This document describes two examples that use LVDS IP, following is the detail of examples: Example 1: LCD color bar by LVDS TX

? Generate the color bar RGB and DE signals, then push these data into LVDS TX parallel data input to

drive a LVDS LCD.

? With TX sclk or pixel clock 65MHz, edge clock 227.5MHz, serial/deserial-factor 7, 1 clock channel and 4 data channels.

Example 2: LVDS self TX and RX

? Outside the board loop LVDS TX back to LVDS RX pads, and inside FPGA, send a const into LVDS TX

parallel data input, and check the received parallel data from LVDS RX.

? With TX/RX sclk clock 60MHz, edge clock 210MHz, serial/deserial-factor 7, 1 clock channel and 1

data channel.

Device: CME-HR3

3

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User Guide of LVDS example

2 The example detail

2.1 Function description

2.1.1 Example 1

This example(lvds_colorbar.zip) is to drive a lvds LCD color bar(1024x768) through HR3 LVDS TX, and following figure is general structure of the example:

Figure 2-1 LVDS IP TX driving LCD color bar example block diagram

This case consists of 3 parts as shown in above figure 2-1: Color Bar RGB&DE generator, LVDS TX, and PLL.

1. Color Bar RGB&DE generator:

This block generates the color bar RGB and DE signals, then push these data into LVDS TX parallel data inputs. The LCD resolution can be changed through changing RTL of this module.

2. LVDS TX:

This block serializes the input parallel data into LVDS signals, driving the LVDS LCD, the LVDS TX contains 1 clock channel and 4 data channels, with TX sclk or pixel clock 65MHz, edge clock 227.5MHz, serial-factor 7.

Following is the configuration of LVDS TX: 4

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User

Guide of LVDS example

3. PLL:

This block generates the 65MHz sclk, and the 227.5MHz eclk. Following is the configuration of PLL:

5