Feedback-Type Dead-Time Compensation Method

A Feedback-Type Dead-Time Compensation Method

for High-Frequency PWM Inverter -Delay and Pulse Width Characteristics-

Masashi Ogawa, Satoshi Ogasawara, Masatsugu Takemoto

Hokkaido University Sapporo, Japan

Abstract—This paper discusses a dead-time compensation method for high-frequency pulse-width modulation (PWM) inverters. Feedback-type dead-time compensation can eliminate error in the inverter output voltage. With next-generation switching devices using SiC, the switching frequency of inverters is expected to improve to 10-fold that of conventional inverters. However, as switching frequency increases, dead time will more strongly affect output voltage error. This paper proposes a new compensation method, which can reduce the minimum output pulse width and the phase delay of the inverter output voltage. An experimental system was constructed and tested, using high-speed power MOSFETs and a field-programmable gate array controller. Experimental results support the validity and usefulness of the proposed compensation method.

causes error in the inverter output voltage, because the dead time alters the timing when the inverter output voltage varies stepwise, depending on the polarity of output current. To eliminate this voltage error, dead-time compensation methods have been researched which can be classified into two types: feedforward[4]-[6] and feedback[7]-[6].

Feedforward-type dead-time compensation operates in accordance with current or polarity, and can be implemented using a simple circuit. However, such methods cannot completely compensate for the dead time if the compensation value is different from the actual voltage error.

In feedback-type dead-time compensation, the compensation value is determined by comparing the actual output voltage with a reference. To implement this method a voltage-detection circuit is required, but the voltage error can be completely eliminated.

This paper proposes a feedback-type dead-time compensation method that aims to improve the pulse width and delay of the output voltage in comparison with conventional compensation methods[5]. An experimental system was constructed and tested, using high-speed power MOSFETs and a field-programmable gate array (FPGA) controller. Experimental results support the validity and usefulness of the proposed compensation method.

I. INTRODUCTION

Pulse-width modulation (PWM) inverters are now widely used in many applications (e.g., adjustable-speed drives). Development of power switching devices such as insulated-gate bipolar transistors (IGBTs) has improved the switching frequency of PWM inverters. With next-generation switching devices using SiC or GaN, the switching frequency of inverters is expected to improve to 10-fold that of inverters using conventional IGBTs. Higher switching frequency improves inverter performance, but causes electromagnetic interference (EMI) and voltage distortion. A major source of EMI is common-mode noise, and many researchers have investigated methods employing an active circuit to eliminating such noise[1]-[3]. The voltage distortion is generated by dead time, which is essential for PWM inverters. To eliminate the voltage distortion, many dead-time compensation methods have been proposed[4]-[10].

II. FEEDBACK-TYPE DEAD-TIME COMPENSATION Fig. 1 shows the system configuration for feedback-type compensation. A compensation circuit compares input signal A with feedback signal B to generate compensated signal C. A dead-time-inserting circuit inputs compensated signal C and

If upper and lower switches in one phase of a voltage inserts dead time into signals D and E of the upper and lower source inverter are turned on simultaneously, the phase of the gates, respectively. Each gate drive circuit drives a switching inverter is shorted and the inverter may fail. To prevent a short device by signals D and E. The detection circuit detects output circuit, the gate signals of the inverter introduce dead time, voltage signal F and feeds it back to the compensation circuit. which is the duration that both the upper and lower switches Fig. 2 shows the respective signals in feedback-type are turned off during current commutation. Inserting dead time compensation. D is the compensation time for correcting the

c

978-1-4577-1216-6/12/$26.00 ©2012 IEEE100

voltage error. When signal C is turned on, signal E turns off immediately and signal D turns on after the dead time td has elapsed. Delay time is included in the gate drive circuits and power switching devices. Moreover, general power switching devices have different delay times for turning on and off. Dg1 is the turn-on delay and Dg2 is the turn-off delay with respect to the gate signal for device operation. In bipolar devices, Dg2 is longer than Dg1 because of storage time. Signal B is fed back to the compensation circuit after delay time Dd of the detection circuit.

Each compensation method is characterized by how to adjust Dc. Murai et al. proposed an excellent compensation method, which we adopt as a standard for comparison[7]. Here, we refer to their method as the conventional method. III. CONVENTIONAL METHOD

Fig. 3 shows the operation of the conventional method. An internal counter (IC) included in the compensation circuit adjusts the state of signal C, depending on the state of signals A and B. IC operates just after each pulse edge of input signal A. In Fig. 3, d1 is a time delay from the first turn-off of C for feedback signal B, which relates to the voltage error of the

inverter. The IC decrements d1, and keeps this value until the next turn-on of signal A. By means of IC, the compensated signal C turns on after delay d1 from when signal A turns on. The delay operation corresponds to compensating for the voltage error generated by d1.

On the other hand, signal B turns on after d2 from when signal C turns on. IC also increments d2, and keeps this value until the next time signal A is turned off. Delaying the next turn-off of signal C by d2 with respect to signal A corresponds to compensating for the voltage error generated by d2. By repeating this operation, voltage error caused by dead time can be completely eliminated.

However, the conventional method has two problems. The first problem is that the delay time from A to B is relatively long. The second problem is that the minimum output pulse width is limited. Both the delay time from A to B and the minimum pulse width of input signal A can be estimated as the sum of turn-on and turn-off delays, d1 + d2. These problems make it difficult to apply the conventional method to PWM inverters operating at a high switching frequency.

A C

D E Upper

Fig. 1. System configuration of for feedback-type

dead-time compensation

count

A

delay

count delay count

Lower

F(i>0)

B

B(i>0)

IC

F(i<0)

C

Fig. 3. Conventional method

B(i<0)

Fig. 2. Signals in feedback-type compensation

101

immediately and the EC value is set as X. Feedback signal B is turned off after delay d2 from when signal A is turned off. A. Normal Compensation From the moment that signal A is turned on for a second time, Figs. 4 and 5 show operation of the proposed method. An the compensation keeps signal C turned off as long as the EC

error counter (EC) included in the compensation circuit value is less than X. The delay time between signals A and C operates depending on the state of signals A and B, as shown equals d2 - d1. Assuming that d3 = d1, the pulse width of B (T6 in Table 1. The proposed method is characterized by – T4) becomes equal to the pulse width of A (T5 – T3). Times sophisticated operation of the error counter, which is T1 through T6 are shown in Fig. 4. If turn-on delay d1 is equivalent to integration of the voltage error at the inverter longer than turn-off delay d2, the proposed method operates as output. Only the moment of switching the output voltage is shown in Fig. 5. When input signal A is first turned off, the detected by the detection circuit, and the error counter EC value is set as Y. When signal A turns on for a second increments or decrements, corresponding to the detected time, C turns on immediately because the EC value is not signal B and the input signal A. Therefore, the counter value greater than Y. From the moment that signal A is turned off corresponds to the integral of output voltage error assuming a for a second time, the compensation keeps signal C turned on constant dc-link voltage. Delaying C with respect to A can as long as the EC value is greater than Y. Assuming that d2= compensate for the voltage error. When the counter value is Table 1. Operation of EC negative, compensation is carried out when signal A is turned on. Conversely, when the counter value is positive, compensation is carried out when signal A is turned off. IV. PROPOSED METHOD

If turn-on delay d1 is shorter than turn-off delay d2, the proposed method operates as shown in Fig. 4. When signal A is first turned on, compensated signal C is turned on

T1 T2 T3 T4 T5 T6

A A S1 S2 S3 S4 S5 S6

B B

EC Y

X Y EC X

C C

Fig. 4. Proposed method (d1<d2) U1 U2 U3

U4 U5 Fig. 5. Proposed method (d1>d2)

A B Y

EC X

C

Fig. 6. Proposed method (short pulse) 102

d4, the pulse width of B (S6 - S4) becomes equal to the pulse width of A (S5 – S3), where times S1 through S6 are shown in Fig. 5, by delaying the moment when C turns off. As a result, the compensation circuit performs the following actions. ?

When signal A is turned on:

If the EC value is less than X, turn-on of signal C is delayed until the EC value become X. Otherwise, signal C is turned on immediately.

When signal A is turned off:

If the EC value is greater than Y, turn-off of signal C is delayed until the EC value become Y. Otherwise, signal C is turned off immediately.

DC supply

Input signal

Inverter

FPGA controller and detection circuit

?

Fig. 7. Experimental system

P 1 Upper

i

P 0

54 Ω Lower P 2

Fig. 8. Main circuit of the experimental system

2 mH

Therefore, the delay time from A to B and the minimum pulse width are the turn-on delay d1 or turn-off delay d2, whichever is larger. As a result, both the delay time and the minimum pulse width can be reduced in comparison with the conventional method.

B. Short-Pulse Compensation

Fig. 6 depicts the operation when the compensation circuit inputs short pulses, the width of which is shorter than the minimum output pulse (times U1 through U5 are shown in the figure). Here, we assume that d2 is greater than d1. When the input signal A is turned on at U1, the compensated signal C is not turned on, because the EC value is less than X. The next time signal A is turned off (U2), signal C is turned off immediately, because the EC value is less than Y. Since the short pulse in signal A is lost in signal C, the corresponding pulse disappears in signal B. However, the voltage error is integrated by EC. Even if the signal C pulse is not lost but shorter than the dead time, the corresponding pulse may disappear in signal B as shown in Fig. 6. When the EC value is greater than Y, a pulse certainly appears in signal B, because signal C is kept on until signal B turns on. Consequently, the pulse width of signal B (U5 - U4) becomes almost equal to the sum of the pulse widths within the period between U3 and U1, and the proposed method can compensate for the voltage error generated by the dead time. If short negative pulses are input, the compensation method performs similarly, as shown in Fig. 6.

II.

EXPERIMENT

F

Turn-on

i

F

Turn-off

Fig. 9. Detection circuit

A. Experimental System

The conventional method and the proposed method are applied to an experimental system. The compensation circuit and the dead-time-inserting circuit are implemented in an FPGA, the clock frequency of which is 100 MHz. High-speed power MOSFETs are used for the switching devices, because these can operate faster than IGBTs.

Fig. 7 shows the experimental system. This system has the same composition as in Fig. 1. Fig. 8 shows the main circuit of the experimental system. Corresponding to connection of the P0, P1, and P2 terminals, experiments are performed under no-load, positive current, and negative current conditions.

i

Turn-on

Turn-off

Fig. 10. Operation waveforms of detection circuit

103

capacitor Fig. 9 shows circuit the and detection two photocouplers. circuit consisting This of a circuit resistor-is connected inverter and between the neutral the point output of the terminal dc-link of voltage. a half-bridge Fig. 10 shows the operation waveforms of this detection circuit, which has the following advantages:

? Power loss continuous, but pulsewise. is low, because the resistor current is not ? Detection rise time error and fall caused time by of the difference the photocoupler between the can be eliminated.

The detection circuit used in the conventional method is composed of a resistor and a photocoupler[7]. Since a general-purpose photocoupler has different delay times at turn-on and turn-off, detection error occurs. Moreover, continuous current flowing in the resistor will cause large power loss.

In this experiment, the delay time of the gate drive circuit Dtime g1, the tdelay time of the detection circuit Dd, and the dead d are 0.56 μs, 0.23 μs, and 0.95 μs, respectively.

B. Comparison with Conventional Method (no load)

conventional and proposed methods under no-load condition, Figs. 11 and 12 show the experimental results of the where Fig. 11, the minimum the output pulse output width pulse of each method is minimal. In width and the delay time Drespectively. af of the conventional The minimum method output are 3.60 pulse μs width and 3.26 of μs, the conventional method is the sum of conventional method corresponds to the Dc, td, Dprevious delay g, and Dd. Dc of the time, which conventional method, delay is equal to the sum time of Dtd, Dg1,t and D+ d. DIn the is 2(tab is 2(d + Dg1 d) and Dafd + Dg1) + Dd.

As shown in Fig. 12, the minimum output pulse width and the delay time μs and 1.51 μs, respectively. Daf of the proposed method are reduced to 1.50 A minimum output pulse width of proposed method, delay time the proposed method is the Dsum of td and DDg1. In the

is zero. af is the sum of c, td, and Dbut Dg1 c

C. Short-Pulse Compensation (no load)

Fig. 13 shows the experimental results when very short pulses enlarged are view. given Some as the output input pulses signal, disappear, and Fig. 14 because shows the an input pulse width is shorter than the minimum width. However, pulse width of the output voltage is equal to the sum of the input can completely pulses that compensate disappear. Therefore, for the average the proposed output method voltage even under short-pulse conditions.

D. Influence of Current Polarity

Figs. 15, 16, and 17 show the experimental results in no-load, positive current, and negative current conditions. The input pulse width of 3 μs is the same. Regardless of the output current conditions, the pulse width of the output voltage is the same as that of the input signal and the delay time is almost constant, even though the gate signals are modified by the compensation circuit. Therefore, these experimental

results

104Fig. 11. Minimum output pulse width of conventional method Fig. 12. Minimum output pulse width of proposed method Fig. 13. Short-pulse compensation Fig. 14. Short-pulse compensation (enlarged view)