Chapter1 Computer System Overview

CHAPTER 1 COMPUTER SYSTEM OVERVIEW

REVIEW QUESTIONS

1.1 List and briefly define the four main elements of a computer.

1.2 Define the two main categories of processor registers.

1.3 In general terms, what are the four distinct actions that a machine instruction can specify?

1.4 What is an interrupt?

1.5 How are multiple interrupts dealt with?

1.6 What characteristics distinguish the various elements of a memory hierarchy?

1.7 What is cache memory?

1.8 List and briefly define three techniques for I/O operations.

1.9 What is the distinction between spatial locality and temporal locality?

1.10 In general, what are the strategies for exploiting spatial locality and temporal locality?

PROBLEMS

1.1 Suppose the hypothetical processor of Figure 1.3 also has two I/O instructions:

0011 = Load AC from I/O

0111 = Store AC to I/O

In these cases, the 12-bit address identifies a particular external device. Show the program execution (using format of Figure 1.4) for the following program:

1. Load AC from device 5.

2. Add contents of memory location 940.

3. Store AC to device 6.

Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.

1.2 The program execution of Figure 1.4 is described in the text using six steps. Expand this description to show the use of the MAR and MBR.

1.3 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields. The first byte contains the opcode and the remainder an immediate operand or an operand address.

a. What is the maximum directly addressable memory capacity (in bytes)? b. Discuss the impact on the system speed if the microprocessor bus has

1. a 32-bit local address bus and a 16-bit local data bus, or

2. a 16-bit local address bus and a 16-bit local data bus.

c. How many bits are needed for the program counter and the instruction register?

1.4 Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.

a. What is the maximum memory address space that the processor can access directly if it is connected to a “16-bit memory”?

b. What is the maximum memory address space that the processor can access

directly if it is connected to an “8-bit memory”?

c. What architectural features will allow this microprocessor to access a separate

“I/O space”?

d. If an input and an output instruction can specify an 8-bit I/O port number, how

many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O

ports? Explain.

1.5 Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an

8-MHz input clock. Assume that this microprocessor has a bus cycle whose

minimum duration equals four input clock cycles. What is the maximum data

transfer rate across the bus that this microprocessor can sustain in bytes/s? To

increase its performance, would it be better to make its external data bus 32 bits

or to double the external clock frequency supplied to the microprocessor? State

any other assumptions you make and explain. Hint: Determine the number of

bytes that can be transferred per bus cycle.

1.6 Consider a computer system that contains an I/O module controlling a simple

keyboard/ printer Teletype. The following registers are contained in the CPU and

connected directly to the system bus:

INPR: Input Register, 8 bits

OUTR: Output Register, 8 bits

FGI: Input Flag, 1 bit

FGO: Output Flag, 1 bit

IEN: Interrupt Enable, 1 bit

Keystroke input from the Teletype and output to the printer are controlled by the I/O

module. The Teletype is able to encode an alphanumeric symbol to an 8-bit word

and decode an 8-bit word into an alphanumeric symbol. The Input flag is set

when an 8-bit word enters the input register from the Teletype. The Output flag is

set when a word is printed.

a. Describe how the CPU, using the first four registers listed in this problem, can

achieve I/O with the Teletype.

b. Describe how the function can be performed more efficiently by also employing

IEN.

1.7 In virtually all systems that include DMA modules, DMA access to main memory

is given higher priority than processor access to main memory. Why?

1.8 A DMA module is transferring characters to main memory from an external

device transmitting at 9600 bits per second (bps).The processor can fetch

instructions at the rate of 1 million instructions per second. By how much will the

processor be slowed down due to the DMA activity?

1.9 A computer consists of a CPU and an I/O device D connected to main memory M

via a shared bus with a data bus width of one word. The CPU can execute a

maximum of 106 instructions per second. An average instruction requires five

processor cycles, three of which use the memory bus. A memory read or write

operation uses one processor cycle. Suppose that the CPU is continuously

executing “background” programs that require 95% of its instruction execution

rate but not any I/O instructions. Assume that one processor cycle equals one bus

cycle. Now suppose that very large blocks of data are to be transferred between

M and D.

a. If programmed I/O is used and each one-word I/O transfer requires the CPU to execute two instructions, estimate the maximum I/O data transfer rate, in words per second, possible through D.

b. Estimate the same rate if DMA transfer is used.

1.10 Consider the following code:

for (i = 0; i < 20; i++)

for (j = 0; j<10; j++)

a[i] = a[i] * j

a. Give one example of the spatial locality in the code.

b. Give one example of the temporal locality in the code.

1.11 Generalize Equations (1.1) and (1.2) in Appendix 1 A to n-level memory hierarchies.

1.12 Consider a memory system with the following parameters:

Tc = 100 ns Cc = 0.01 cents/bit

Tm = 1200 ns Cm = 0.001 cents/bit

a. What is the cost of 1 MByte of main memory?

b. What is the cost of 1 MByte of main memory using cache memory

technology?

c. If the effective access time is 10% greater than the cache access time, what is

the hit ratio H?

1.13 A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main

memory but not in the cache, 60 ns are needed to load it into the cache (this

includes the time to originally check the cache), and then the reference is started

again. If the word is not in main memory, 12 ms are required to fetch the word

from disk, followed by 60 ns to copy it to the cache, and then the reference is

started again. The cache hit ratio is 0.9 and the main-memory hit ratio is 0.6.What

is the average time in ns required to access a referenced word on this system?

1.14 Suppose a stack is to be used by the processor to manage procedure calls and returns. Can the program counter be eliminated by using the top of the stack as a program counter?

ANSWERS TO QUESTIONS

1.1 List and briefly define the four main elements of a computer.

A main memory, which stores both data and instructions: an arithmetic and logic unit (ALU) capable of operating on binary data; a control unit, which interprets

the instructions in memory and causes them to be executed; and input and output (I/O) equipment operated by the control unit.

1.2 Define the two main categories of processor registers.

User-visible registers: Enable the machine- or assembly-language programmer to minimize main memory references by optimizing register use. For high-level

languages, an optimizing compiler will attempt to make intelligent choices of

which variables to assign to registers and which to main memory locations. Some high-level languages, such as C, allow the programmer to suggest to the compiler which variables should be held in registers. Control and status registers: Used by the processor to control the operation of the processor and by privileged,

operating system routines to control the execution of programs.

1.3 In general terms, what are the four distinct actions that a machine instruction can specify? These actions fall into four categories: Processor-memory: Data may be

transferred from processor to memory or from memory to processor. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. Data processing: The processor may perform some arithmetic or logic operation on data. Control: An instruction may specify that the sequence of execution be altered.

1.4 What is an interrupt?

An interrupt is a mechanism by which other modules (I/O, memory) may interrupt the normal sequencing of the processor.

1.5 How are multiple interrupts dealt with?

Two approaches can be taken to dealing with multiple interrupts. The first is to

disable interrupts while an interrupt is being processed. A second approach is to

define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be interrupted.

1.6 What characteristics distinguish the various elements of a memory hierarchy? The three key characteristics of memory are cost, capacity, and access time.

1.7 What is cache memory?

Cache memory is a memory that is smaller and faster than main memory and that

is interposed between the processor and main memory. The cache acts as a buffer

for recently used memory locations.

1.8 List and briefly define three techniques for I/O operations.

Programmed I/O: The processor issues an I/O command, on behalf of a process,

to an I/O module; that process then busy-waits for the operation to be completed

before proceeding. Interrupt-driven I/O: The processor issues an I/O command

on behalf of a process, continues to execute subsequent instructions, and is

interrupted by the I/O module when the latter has completed its work. The

subsequent instructions may be in the same process, if it is not necessary for that

process to wait for the completion of the I/O. Otherwise, the process is suspended

pending the interrupt and other work is performed. Direct memory access (DMA):

A DMA module controls the exchange of data between main memory and an I/O

module. The processor sends a request for the transfer of a block of data to the

DMA module and is interrupted only after the entire block has been transferred.

1.9 What is the distinction between spatial locality and temporal locality?

Spatial locality refers to the tendency of execution to involve a number of

memory locations that are clustered. Temporal locality refers to the tendency for

a processor to access memory locations that have been used recently.

1.10 In general, what are the strategies for exploiting spatial locality and temporal

locality?

Spatial locality is generally exploited by using larger cache blocks and by

incorporating prefetching mechanisms (fetching items of anticipated use) into

the cache control logic. Temporal locality is exploited by keeping recently used

instruction and data values in cache memory and by exploiting a cache

hierarchy.