RAM块仿真——FPGA

FPGA中RAM块仿真程序,包含源代码和TB程序

Ram块例程

library ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY RAM IS

PORT(clock:IN std_logic;

data:IN std_logic_vector(15 DOWNTO 0);

address:IN std_logic_vector(5 DOWNTO 0);

wren:IN std_logic;

outx:out std_logic;

q:OUT std_logic_vector(15 DOWNTO 0));

END ram;

ARCHITECTURE behav OF RAM IS

TYPE mem IS ARRAY(0 TO 63) OF std_logic_vector(15 DOWNTO 0); SIGNAL ram_block:mem;

SIGNAL reg:std_logic_vector(15 DOWNTO 0);

signal ot:std_logic:='0';

BEGIN

outx<=ot;

PROCESS(clock,address)

VARIABLE ads:integer RANGE 0 TO 63;

BEGIN

ot<=not ot;

ads:=conv_integer(address);

-- ads:=0;

IF(clock'event AND clock='1')THEN

IF(wren='1')THEN

ram_block(ads)<=data;

ELSE

FPGA中RAM块仿真程序,包含源代码和TB程序

reg<=ram_block(ads);

END IF;

END IF;

END PROCESS;

q<=reg;

END behav;

Ram块调用例程

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity div10_tb is

end div10_tb;

architecture one of div10_tb is

component RAM is

port(clock:IN std_logic;

data:IN std_logic_vector(15 DOWNTO 0);

address:IN std_logic_vector(5 DOWNTO 0);

wren:IN std_logic;

outx:out std_logic;

q:OUT std_logic_vector(15 DOWNTO 0));

end component;

signal clk :std_logic:='0';

SIGNAL data: std_logic_vector(15 DOWNTO 0);

SIGNAL address: std_logic_vector(5 DOWNTO 0);

SIGNAL wren: std_logic;

SIGNAL q: std_logic_vector(15 DOWNTO 0);

signal outx:std_logic;

FPGA中RAM块仿真程序,包含源代码和TB程序

constant clk_period:time:=20 ns;

begin

uU2: RAM port map (clock=>clk,data=>data,address=>address,wren=>wren,outx=>outx,q=>q); process

variable jisu:integer:=0;

begin

wait for clk_period/2;

clk<='1';

jisu:=jisu+1;

if(jisu>30) then

jisu:=0;

end if;

if(jisu >= 1)and (jisu<= 6) then

wren<='1';

address<="000001";

data<="1010101010101010";

elsif(jisu >= 7)and (jisu<= 12) then

wren<='1';

address<="000010";

data<="0101010101010101";

elsif(jisu >= 13)and (jisu<= 14) then

wren<='0';

address<="000000";

data<="0000000000000000";

FPGA中RAM块仿真程序,包含源代码和TB程序

elsif(jisu >= 15)and (jisu<= 20) then wren<='0';

address<="000010";

elsif(jisu >= 21)and (jisu<= 26) then wren<='0';

address<="000001";

else

address<="000000";

data<="0000000000000000";

wren<='Z';

end if;

wait for clk_period/2; clk<='0'; end process; end;