ADP3186电源管理芯片

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5-Bit Programmable 2-/3-/4-Phase

FEATURES

Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase

±1% worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers

Active current balancing between all output phases

Built-in power good/crowbar blanking supports on-the-fly VID code changes

5-bit digitally programmable 0.8 V to 1.55 V output

Programmable short-circuit protection with programmable latch-off delay

APPLICATIONS

Desktop PC power supplies for AMD Opteron? processors VRM modules

GENERAL DESCRIPTION

The ADP3186 is a highly efficient multiphase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the pro-cessor, which is used to set the output voltage between 0.8 V and 1.55 V. It uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relation-ship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing the construction of up to four complementary buck switching stages.

The ADP3186 includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so that it is always optimally positioned for a system transient. The ADP3186 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a power good output that accommodates on-the-fly output voltage changes requested by the CPU.

The ADP3186 is specified over the commercial temperature range of 0°C to 85°C and is available in 28-lead TSSOP and QSOP packages.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Synchronous Buck Controller

ADP3186

FUNCTIONAL BLOCK DIAGRAM

PWM1

PWM2

PWM3

PWM4

SW1

SW2SW3

SW4

CSSUM

CSREF

CSCOMP

FB

1

00-0-41940Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 http://wendang.chazidian.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

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ADP3186

TABLE OF CONTENTS

Features..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Specifications.....................................................................................3 Test Circuits.......................................................................................5 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Pin Configuration and Function Descriptions.............................7 Typical Performance Characteristics.............................................8 Theory of Operation........................................................................9 Start-Up Sequence........................................................................9 Master Clock Frequency..............................................................9 Output Voltage Differential Sensing..........................................9 Output Current Sensing..............................................................9 Active Impedance Control Mode.............................................10 Current Control Mode and Thermal Balance........................10 Voltage Control Mode................................................................10 Soft Start......................................................................................10 Current Limit, Short-Circuit, and Latch-Off Protection......11 Dynamic VID..............................................................................11 Power Good Monitoring...........................................................12 Output Crowbar.........................................................................12 Output Enable and UVLO........................................................12 Application Information................................................................14

Setting the Clock Frequency.....................................................14 Soft Start and Current Limit Latch-Off Delay Times............14 Inductor Selection......................................................................14 Designing an Inductor...............................................................15 Selecting a Standard Inductor..............................................15 Output Droop Resistance..........................................................15 Inductor DCR Temperature Correction.................................16 Output Offset..............................................................................16 COUT Selection.............................................................................17 Power MOSFETs.........................................................................17 Ramp Resistor Selection............................................................18 COMP Pin Ramp.......................................................................19 Current Limit Setpoint..............................................................19 Feedback Loop Compensation Design....................................19 CIN Selection and Input Current di/dt Reduction..................20 Tuning Procedure.......................................................................21 DC Loadline Setting..............................................................21 AC Loadline Setting...............................................................21 Initial Transient Setting.........................................................22 Layout and Component Placement.........................................22 General Recommendations..................................................22 Power Circuitry Recommendations....................................23 Signal Circuitry Recommendations....................................23 Outline Dimensions.......................................................................24 Ordering Guide..........................................................................24

REVISION HISTORY

3/06—Rev. 0 to Rev. A

Updated ADP3110 to ADP3110A.................................Universal Changes to Table 1..........................................................................3 Added QSOP Package..................................................................24 Updated Ordering Guide.............................................................24 8/04—Revision Sp0: Initial Version

Rev. A | Page 2 of 24

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ADP3186

SPECIFICATIONS

VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise specified.1

Table 1. Unit ERROR AMPLIFIER Output Voltage Range2VCOMP 0.5 FB

0.8 V Output Referenced to FBRTN,

CSSUM = CSCOMP, Figure 2

TSSOP 0.7920 QSOP 0.7880 1.175 V Output Referenced to FBRTN,

CSSUM = CSCOMP, Figure 2

TSSOP 1.1633 QSOP 1.1574 1.55 V Output Referenced to FBRTN,

CSSUM = CSCOMP, Figure 2

TSSOP 1.5345 QSOP 1.5268 Line Regulation VCC = 10 V to 14 V 0.05 % ΔVFB

Input Bias Current IFBμA

FBRTN Current IFBRTNμA

Output Current IO(ERR)FB Forced to VOUT – 3% 500 μA

Gain Bandwidth Product GBW(ERR)COMP = FB 20 MHz

Slew Rate CCOMP = 10 pF 25 V/μs

VID INPUTS

Input Low Voltage VIL(VID) V

Input High Voltage VIH(VID) 1.5 Input Current, Input Voltage Low IIL(VID)VID(X) = 0 V 20 26 μA

Pull-Up Resistance RVID 100 120 kΩ

Internal Pull-Up Voltage V

VID Transition Delay Time2 VID code change to FB change 400 ns

400 No CPU Detection Turn-Off Delay VID code change to 11111 to PWM

2Timegoing low

OSCILLATOR 2Frequency RangefOSCMHz Frequency Variation fPHASETA = 25°C, RT = 250 kΩ, 4-phase 155 200 245 kHz

TA = 25°C, RT = 115 kΩ, 4-phase 400 kHz

TA = 25°C, RT = 75 kΩ, 4-phase 600 kHz

Output Voltage VRTRT = 100 kΩ to GND 1.9 2.0 2.1 V

Timing Resistor Value kΩ

RAMPADJ Output Voltage VRAMPADJRAMPADJ – FB ?50 +50 mV

RAMPADJ Input Current Range IRAMPADJμA

CURRENT SENSE AMPLIFIER Offset Voltage VOS(CSA)CSSUM – CSREF, Figure 3

TSSOP ?3 QSOP ?3.5 Input Bias Current IBIAS(CSSUM) ?50 Gain Bandwidth Product GBW(CSA) 10 Slew Rate CCSCOMP = 10 pF 10 V/μs

Input Common-Mode Range CSSUM and CSREF 0 2.7 V

Rev. A | Page 3 of 24

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ADP3186

Unit Positioning Accuracy Figure 4ΔVFBOutput Voltage Range 0.05 2.7 V Output Current ICSCOMPμA CURRENT BALANCE CIRCUIT Common-Mode Range VSW(X)CM ?600 Input Resistance RSW(X)SW(X) = 0 V Input Current ISW(X)SW(X) = 0 V 4 7 10 μA Input Current Matching SW(X) = 0 V ?5 +5 % ΔISW(X)CURRENT LIMIT Output Voltage

Normal Mode VILIMIT(NM)EN > 2.0 V, RILIMIT = 250 kΩ Shutdown Mode VILIMIT(SD)EN < 0.8 V, IILIMIT = ?100 μA Output Current, Normal Mode IILIMIT(NM)EN > 2.0 V, RILIMIT = 250 kΩ Maximum Output Current2Current Limit Threshold Voltage VCLVCSREF – VCSCOMP, RILIMIT = 250 kΩ Current Limit Setting Ratio VCL/IILIMITDELAY Normal Mode Voltage VDELAY(NM)RDELAY = 250 kΩ DELAY Overcurrent Threshold VDELAY(OC)RDELAY = 250 kΩ Latch-Off Delay Time tDELAYRDELAY = 250 kΩ, CDELAY = 12 nF SOFT START Output Current, Soft Start Mode IDELAY(SS)During startup, DELAY < 2.8 V Soft Start Delay Time tDELAY(SS)RDELAY = 250 kΩ, CDELAY = 12 nF,

VID code = 011111

ENABLE INPUT Input Low Voltage VIL(EN) Input High Voltage VIH(EN) Input Current, Input Voltage Low IIL(EN)EN = 0 V POWER GOOD Undervoltage Threshold Overvoltage Threshold Output Low Voltage

OFF_State Leakage Current Power Good Delay Time VID Code Changing VID Code Static Crowbar Trip Point Crowbar Reset Point Crowbar Delay Time VID Code Changing VID Code Static PWM OUTPUTS

Output Low Voltage Output High Voltage SUPPLY DC Supply Current

UVLO Threshold Voltage UVLO Hysteresis

12

2.9 3 3.1 V mV 12 μA 60 μA 105 125 145 mV 10.4 mV/μA 2.9 3 3.1 V 1.7 1.8 1.9 V 1.5 ms

15 20 25 μA 1 V 2.0 ?1 +1 μA

?200 ?300 ?400 mV 200 300 400 mV 150 400 mV μA

100 250 μs 200 ns

100 250 μs 400 ns 4.0 5 V 5 10 mA

VPWRGD(UV)VPWRGD(OV)VOL(PWRGD)

VCROWBAR tCROWBAR

VOL(PWM)VOH(PWM)

Relative to nominal DAC output Relative to nominal DAC output IPWRGD(SINK) = 4 mA VCSREF = VDAC

Overvoltage to PWM going low

IPWM(SINK) = ?400 μA IPWM(SOURCE) = +400 μA

VUVLOVCC rising

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

Guaranteed by design or bench characterization, not production tested.

Rev. A | Page 4 of 24

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TEST CIRCUITS

2

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Figure 2. Closed-Loop Output Voltage Accuracy

39k1k1.0V

3

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Figure 3. Current Sense Amplifier, VOS

Rev. A | Page 5 of 24

ADP3186

200k1.0V

Figure 4. Positioning Voltage